Abstract: A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. A new low power test pattern generator using linear feedback shift register (LFSR), called LP-TPG, and is presented to reduce the average power and peak power of the circuit by reducing the switching activities during test. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using, a synchronous pipelined 4x4 and 8x8 Braun array multipliers. The system-on chip (SoC) approach is adopted for implementation on Xilinx Field Programmable Gate Arrays (FPGAs). From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.
Keywords: BIST, Test Pattern Generator, LFSR, FPGA.