Abstract: This Paper focuses on the realization and implementation of an efficient logic design of a convolutional encoder and adaptive Viterbi decoder (AVD) called cryptosystem with a constraint length, K of 3 and a code rate (k/n) of 1/2 using field programmable gate array (FPGA) technology. The adaptive viterbi decoder with convolutional encoder is a powerful forward error correction technique. This technique is particularly suited to a channel where the transmitted data is corrupted by additive white Gaussian noise. Viterbi algorithm is a maximum-likelihood algorithm for decoding of convolutional codes and these codes have good correcting capability and perform well on every noisy channel. In this paper viterbi decoder is designed for faster decoding speed and less are routing area. The proposed system is realized using verilog HDL and simulation is done by using modelsim SE 6.4c and Xilinx is used for RTL Design.
Keywords: Convolutional Encoder, Viterbi Decoder, Verilog HDL, FPGA.