Abstract: In many of digital systems like graphic processors, digital signal processors fast parallel multiplication using adder trees are present. To speed up the computation like addition is very important. This paper presents different approaches to the efficient implementation of compress tree adders on FPGAs. Through a fair comparison we present a proper compressor selection approach to get minimum XOR delay. This paper will help to choose a proper compressor for fast multiplication. This approach is defined in parameterizable HDL code, which makes it compatible with any FPGA family.


Keywords: Redundant adder, Carry Save addition, multi-operand addition.