Abstract: Carry Select Adder (CSLA) is one of the fastest adder which performs fast arithmetic functions in many data processing processors. A conventional CSLA has less carry propagation delay (CPD) than ripple carry adder (RCA). Carry select adder provide compromise between RCA and carry look ahead adder. For the CSLA new logic is proposed by reducing redundant logic operations present in conventional CSLA. In the proposed scheme the carry select (CS) operation is schedule before calculation of final sum. This is different approach from the conventional. Two carry words (cin = 0 and 1) bit patterns and fixed cin bits is use for generation units and CS logic optimization. Final sum and carry is calculated by using pipelining structure. The proposed work is carried out using Modelsim SE 6.3f and Quatus2 software.
Keywords: Adder, arithmetic unit, low power, CSLA, RCA, low delay, area efficient.