Abstract:  Computers were originally built as fast, reliable and accurate computing machines. It does not matter how large computers get, one of their main tasks will be to always perform computation. Most of these computations need real numbers as an essential category in any real world calculations. Real numbers are not finite; therefore no finite, representation method is capable of representing all real numbers, even within a small range. Thus, most real values will have to be represented in an approximate manner. The scope of this paper includes study and implementation of Adder/Subtractor and Multiplication ,Division and Square root functional units using HDL for computing arithmetic operations and functions suited for hardware implementation. In this paper, we present pipelined architecture to implement Variable bit floating point Arithmetic in Field Programmable Gate Array (FPGA). Specially we designed square root of floating point numbers using modified non restoring square root algorithm.  This algorithm has been optimized by eliminating a number of elements without compromising the precision of the square root and the remainder. The algorithms are coded in VHDL and validated through extensive simulation. These are structured so that they provide the required performance i.e. speed and gate count. It is an improvement over non restoring algorithm as it uses only subtract operation and append 01 instead of add operation and append 11. Here the basic building block is Controlled Subtract Multiplex (CSM). By using this module, the algorithm can be designed for any number of input bits. This strategy offers an efficient use of hardware resources. The modified non restoring algorithm is designed using VHDL and implemented on ALTERA cyclone II FPGA. The implementation results show reduced area in terms of logic elements when compared to restoring algorithm.


Keywords: ALTERA cyclone II FPGA, CSM, VHDL