Abstract: Comparators are the fundamental circuit elements in Analog to digital converters. Efficient design of these comparators with optimizing factors like operational frequency, power consumed per conversion, low voltage input rate, has become a challenge. In this paper, an analysis is presented on single tail comparator, conventional double tail comparator & double tail comparator with reduced leakage power. This presented third circuit particularly carries weight, since the drastic scaling down of transistor size which leads us to consider sub- threshold power leakage. For this we have shown a conventional dynamic double tail comparator using CMOS inverter. The simulation results consolidate the power leakage levels reduced in the proposed circuit. The time delay of final circuit is 2.5ns and the power consumed is 4.5uW.The simulation results are shown in 180nm Technology using Cadence.
Keywords: Double tail comparator, dynamic comparator, reduced leakage, sub-threshold region.