Abstract: Full adder structures are used as a basic and essential blocks to build any VLSI and embedded applications. So it demands the researchers to design low power and low speed full adder circuits to improve efficiency of the design. This project deals with a design of 1-bit hybrid adder circuit by incorporating CMOS and transmission gate logic. Simulations are done using Tanner EDA Tools v.13.0. Parameters of designs like delay and power are measured and power delay product are tabulated and are compared with the prior literatures that includes CMOS logic, CPL, TGA and TFA. Power consumption is found to be decreased and delay also reduced greatly. Also all the adders which are designed from previous literatures and proposed full adder circuits are placed in a 2-bit comparator individually and performance of 2-bit comparator will be analyzed. The comparator designed with proposed full adder circuit shows less power and reduced delay, hence better power delay product compared to others.

Keywords: Comparator, hybrid design, low power, CMOS (Complementary Metal Oxide Semiconductor), high speed, power delay product, Tanner tool.