Abstract: Higher performance, lower cost, increasingly minimizing integrated circuit components, and higher packaging density of chips are ongoing goals of the microelectronics and computer industry. As these goals are being achieved, however, power consumption and flexibility are increasingly becoming bottlenecks that need to be addressed with the new technology in Very Large-Scale Integrated (VLSI) design. Combinational circuits are the heart of electronic devices. Among these combinational circuits the adders are of great importance as these are used at the multiple levels for calculations in functioning of the devices.Coarse-grained reconfigurable architectures (CGRAs) have the potential to offer performance approaching an ASIC with the flexibility, within an application domain, similar to a digital signal processor. In the past, coarse-grained reconfigurable architectures have been encumbered by challenging programming models that are either too farremoved from the hardware to offer reasonable performance or bury the programmer in the minutiae of hardware specification.Theproposed architecture enables the designer to perform efficientDesign Space Exploration. The design can be made adaptable toany of the reconfigurable processor and a similar improvement can be obtained.
Keywords: Adders, low power VLSI, verilog, Spartan-III, FPGA.