Abstract: Designing of low power arithmetic circuit is done considering four levels; algorithm, architecture, circuit and system levels. The most commonly used component of many digital circuit designs is digital multipliers. In order to achieve high data throughput, digital signal processing systems rely on hardware multiplication. There are a number of multipliers available for different applications. This paper focuses on an algorithm, called Canonical Signed Digit Multiplication. This paper presents the performance comparison of the proposed multiplier ie. CSD Multiplier with Array multiplier in terms of power. A Design of 4X4 Multiplier using 90nm Technology is successfully synthesized. Cadence Virtuoso 90nm Technology is used for simulation of the Design. The simulated transient output of 4X4 Multiplier is shown. Multiplier circuit works with 1.8 V power supply. Simulation results obtained show 99.56% reduction in power.

Keywords: Multiplier, Partial Product, Array Multiplier, CSD, Power.