Abstract: The major concern in the designing of low power designs are energy consumption and design flexibility. Power dissipation, delay and area can be reduced with the help of scaling technology. Now a day the devices with ultra low power and area efficient designs are in demand. In this paper CMOS Inverter is presented with ultra low power dissipation which is achieved through scaling of power supply and transistors sizes. This inverter is designed with 180nm Tsmc CMOS technology with supply voltage of 1V and simulation are carried out in PSpice tool. The total power dissipation for this CMOS Inverter is 7.25picowatt.

Keywords: Scaling, Power Delay Product, Subthreshold region, Leakage current.