Abstract: An Efficient tunable subthreshold logic circuit designed by using adaptive feedback equalization circuit. This circuit used in Ladner Fischer adder. This circuit used in a sequential digital logic circuit to mitigate the process variation effects and reduce the dominant leakage energy component in the subthreshold region. Feedback equalizer circuit adjusts the switching threshold of its inverter. It is based on the output of the flip-flop in the previous cycle to reduce the charging and discharging time of the flip-flopís input capacitance. Moreover, the smaller input capacitance of the feedback equalizer reduces the switching time of the last gate in the combinational logic block. Also present detailed energy-performance models of the adaptive feedback equalizer circuit. Proposed approach can reduce the normalized variation of the critical path delay while reducing the energy product at minimum energy supply voltage. This design will be implemented in the 8 bit Ladner Fischer adder and provide the efficient power reduction. The adaptive equalization circuits are design by Verilog HDL and simulated by Modelsim. Area and power will synthesized by Xilinx tool.
Keywords: Feedback equalizer, leakage energy component, subthreshold, parallel prefix adder, Ladner Fischer adder.