Abstract: A Memory-efficient high throughput architecture of arithmetic coder for the set partitioning in hierarchical trees (SPIHT) image compression is proposed in this paper. In this architecture optimizations at different levels of arithmetic coding gives good image compression with high PSNR.

Keywords: Arithmetic coding, Peak Signal to Noise ratio (PSNR), Set Partitioning in Hierarchical Trees (SPIHT), VLSI Arithmetic coder architecture, Wavelet.