A Proposed Wallace Tree Multiplier Using Full Adder and Half Adder

Abstract: The power management has become a great concern due to the increased usage of multimedia devices. Multipliers are the main sources of power consumption in these devices. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. The adder circuit is used as a main component in the multiplier circuits. A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier.A Wallace tree multiplier is a fast multiplies utilize full and half adder in the decrease stage. As far as range and power the execution of XOR-XNOR gates and MUX effective. The proposed method Wallace tree multiplier is far better compare to traditional method.

Keywords: Wallace tree multiplier, Multiplexer, Full adder, Half adder, Cadence tool.