An Improved Design For A High Speed Psuedorandom Bit Generator

Abstract: Pseudorandom bit generator (PRBG) is an essential component for securing data during transmission and storage in various cryptography applications. Among popular existing PRBG methods like linear feedback register (LFSR), linear congruential generator (LCG), coupled LCG (CLCG), and dual-coupled LCG (dual-CLCG), the latter proves to be safer. The hardware implementation of this method features a bottleneck due to the involvement of inequality equations. Initially, a direct architectural mapping of the dual-CLCG method is performed. Since two inequality equations are involved for coupling, it generates pseudorandom bit at unequal interval of your time that results in large variation in output latency. Besides, it consumes an out sized area and fails to realize the maximal period. Hence, to overcome the aforesaid drawbacks, a new efficient PRBG method, i.e., “coupled variable input LCG (CVLCG)”and its architecture came into existence. The novelty of this method is the coupling of two newly formed variable input LCGs that generates pseudorandom bit at every uniform clock rate, attains maximum length sequence and reduces one comparator area as compared to the dual-CLCG architecture. The CVLCG architecture have been modified again to enable cross coupling in order to achieve high speed and more randomness. The proposed Cross- CVLCG architecture is implemented using Verilog-HDL and evaluated for randomness using the NIST standard test tool. Experimental result reports that the method passes the randomness test with a high degree of consistency.

Keywords: Pseudorandom Bit Generator (PRBG); VLSI Architecture; CVLCG Architecture