Comparative study on a low drop-out voltage regulator

Abstract: Today’s LDO (low drop-out voltage regulator) must meet the requirements of various future demands of the portable electronics. To get a new approach towards a design of low drop-out voltage regulator that provides a modern system on chip (SoC) solution and fulfils the present commercial requirements as well as the projected demands of the future, it becomes necessary to study the literature work. The various performance matrices such as minimization of drop-out voltage, low power, low operating voltages, low quiescent currents, fast transient response, high PSR and high packing density have a vital importance in designing of LDO regulator. Furthermore, capacitor less LDO architecture, overcomes the typical load transient and ac stability issues. The designing can be possible with Digital implementation and programmability can be added to become suitable for more applications. Considering the advancement of future technology, regulator can be proposed with the selection of lower order of nm technology. This paper presents the comparative study of literature work that contributes to the research of LDO using CMOS technology and provides different architectures and techniques to make LDO better.

Keywords: Low Drop-Out Voltage Regulator, Low Power, Low quiescent current, PSR.