Design and Implementation of Area Optimized ALU using GDI Technique

Abstract: Area and power are the two vital issues in analog circuit design and synthesis of ULSI and VLSI circu its which depends on various critical design parameters. The purpose of this paper is the design and implementation of an Arith metic Logic Unit (A LU) using area optimizing techniques such as complementary & Gate-Diffusion-input (GDI). The main sub-blocks of ALU are Adder, Subtractor, shifter and Logical Block. Th is work evaluates and compares the performance and optimized area of ALU with Static CMOS techniq ue and GDI technique in 250n m CM OS (1P5M-1 Poly 5 Metal) process technology. Simulat ions are performed by using Tanner EDA 13.2 tools using model file 250n m CMOS technology. At first, using Tanner 13.2 EDA S-Ed it Tool, the circuits are implemented with Static CMOS technology and then with GDI techniques. Simu lations results validate the proposed concept and verify that GDI technique decreases the area used by ALU and increase the speed of ALU.

Keywords: A LU, VLSI, GDI, CMOS, Lo w Po wer, Power Dissipation, Optimized A LU.