Design Approach towards High Performance Memory of 6 Transistors SRAM Cell Using 45nm CMOS Technology

Abstract: Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The amount of memory required in a particular system depends on the type of application, but, in general, the number of transistors utilized for the information (data) storage function is much larger than the number of transistors used in logic operations and for other purposes. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development towards more compact design rules and, consequently, toward higher data storage densities. The trend towards higher memory density and larger storage capacity will continue to push the leading edge of digital system design. The Microwind 3.1 software will allow designing and simulating an integrated circuit at physical description level. The main novelties related to the 45 nm technology are the high-k gate oxide, metal gate and very low-k interconnect dielectric. The effective gate length required for 45 nm technology is 25nm. Low Power (0.211mwatt), high speed static RAM area efficient chip is designed using 45 nm CMOS technology.

Keywords: 6T Static RAM cell, memory, 45nm VLSI technology, low power.