Design of 1-Bit SRAM Cell Using FinFET

Abstract: CMOS technology shows certain limitations as the device is reduced more and more in the nanometre regime out of which power dissipation, current leakages, doping, and channel length is an important issue. FinFET is evolving to be a promising technology in this regard. In this project, designing, modelling and optimizing the 6- TSRAM cell device is done. Intrinsic variations and leakage control in today’s world, is very difficult to achieve, So bulk-Si MOSFETs limit the scaling of SRAM. It is found that 6-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty, read/write in time analysis. Improvement in SNM (signal to noise margin) can be achieved in 6-T FinFET-based SRAM cells. Improvements in SNM as the 6-T cell, making them attractive for low-power, low-voltage applications. The long- channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct- tunnelling leakage and parasitic capacitances degrade the power consumption and access time.

Keywords: CMOS, 6-T SRAM, FinFET, Signal to noise margin, Simulation, Tanner.