Design of a Low Drop-Out Voltage Regulator using VLSI

Abstract: A Low-Voltage Low-Dropout(LDO) Voltage Regulator that can operate with a very small Input–Output Differential Voltage with nm CMOS technology in turn increasing the Packing Density, provides for the new approaches towards power management is proposed. A Simple Symmetric Operational Trans-Conductance Amplifier is used as the Error Amplifier (EA), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the LDO Regulator. In the rail-to-rail output stage of the EA, a Power Noise Cancellation Mechanism is formed, minimizing the size of the Power MOS transistor. These advantages allow the proposed LDO Regulator to operate over a wide range of operating conditions while achieving maximum current efficiency, less output variation for a variable load transient, and effectively appreciable Power Supply Rejection Ratio. The compact area of the proposed LDO regulator leads to a chip area efficient low drop-out Voltage Regulator which finds its applications for portable electronics, i.e. cellular phones, pagers, laptops, etc.

Keywords: 45nm CMOS Technology, Low Drop-Out Voltage Regulator, Low Power, Low quiescent current, PSRR.