Design of BIST with Low Power Test Pattern Generator

Abstract: Mixed mode BIST schemes use pseudo-random patterns to detect most faults. Theoretical analysis suggests that significantly more care bits can be encoded in the seed of a Linear Feedback Shift Register (LFSR). In this paper we implement low power BIST for 32-bit Vedic multiplier. Main aspect of this is to implement low power BIST with increased fault coverage. This use the LFSR as test pattern generator with changing the seed values for every 2 power m cycle, so for this purpose which uses the counter for monitoring the number of cycles. The objective of this work is to reduce power dissipation in BIST with increased fault coverage. Various methods of pattern generation are compared keeping in view of power consumption. For this purpose m bit binary counter & gray code generator is used. Signature analysis is done with the help of Multiple input Signature Register (MISR). The signature of MISR will indicate whether the circuit under test (CUT) i.e Vedic multiplier is faulty or not. The results are tabulated and compared. From the implementation results, Simulation is carried out in Xilinx ISE and the design is implemented using Vertex 5 Field Programmable Gate Array (FPGA).

Keywords: Vedic multiplier, Test Pattern Generation, MISR, CUT.