Design of Efficient Aging-Aware Predictable Multiplier Using Adaptive Hold Logic

Abstract: High speed and low power utilization is critical configuration objectives in VLSI design circuits. Digital multipliers are most important functional unit. The major constraints for delay in any VLSI circuits are latency and throughput .The negative bias temperature instability (NBTI) effect happens when a pMOS transistor is under negative bias (Vgs= -VDD) increasing the threshold voltage of pMOS transistor and decreases the speed. A comparative phenomenon is done for nMOS, positive bias temperature instability, happens when an nMOS transistor is under positive bias. Both impacts will reflect on the performance of transistor speed, and in the long term, the system may fail due to violation of timing therefore in order to maximize the power consumption and delay ,multiplier with adaptive hold logic is used ,the multiplier is able to provide high throughput through variable latency and can adjust the AHL circuit ti mitigate performance degradation that is due to the aging effect . Additionally, the proposed design can be connected to a segment or column bypassing multiplier. The exploratory results demonstrate that our proposed design with 16 × 16 and 32 × 32 section bypassing multipliers can accomplish up to 62.88% and 76.28% execution change, respectively, contrasted and 16×16 and 32×32 fixed -latency section bypassing multipliers. Besides, our proposed design with 16 × 16 and 32 × A32 column bypassing multipliers can accomplish up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers. Furthermore we removed the tristate buffer from the column -bypass multiplier. With the goal that we can decrease the gate count and enhance the efficiency and speed and reduce the power consumption.

Keywords: Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), variable latency.