Low-Power Architectures and Self-Calibration Techniques of DAC for SAR-ADC implementation

Abstract: SAR-ADC is best suited for low power applications where power has a trade-off with speed. Use of redundant circuitry reduces the on chip area making it cost effective. DAC is one of the components of SAR-ADC that introduces error voltage due to mismatch and consumes large power other than comparator. Low power DAC architectures have been studied and analysed. To account for capacitor mismatch issues self-calibration techniques have been discussed and analysed for 14-bit DAC implementation. All the architectures have been analysed for 100KS/s with 1.6MHz clock speed in 180nm technology with supply voltage of 1.8V. EDA tool used for design analysis is Cadence® Spectre®.

Keywords: Successive Approximation Register Analog-to-Digital Converter (SAR-ADC), Digital-to-Analog Converter (DAC), Electronic Design Automation (EDA), Least Significant Bit (LSB), Calibration.