VLSI Implementation of Pipelined FIR Filter

Abstract: This paper proposes to optimize the system speed with minimal cost and hardware by making use of pipelining approach in the designing of FIR filter. The non- pipelined and pipelined FIR filter has been designed using Hardware Description Language (HDL) and a comparative study of both the filter designs using Radix-4 & Radix-8 has been done. The design synthesis and power analysis are carried out using Xilinx ISE 13.1and Synopsis tool, respectively. The concept of pipelining has been incorporated that results in reducing the delay of the FIR filter, thereby enhancing the speed and reducing the power dissipation as compared to the non-pipelined techniques. Simulation validates the results.

Keywords: FIR filter, Booth multiplier, Pipelining, Non-pipelining, Kaiser Window.