A Novel VLSI Design of Hybrid Carry Skip Adder Implementation based on Verilog HDL

Abstract: This paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. We will implement 8 Bit, 16 Bit, and 32 Bit Existing and Proposed adders. Now we are proposing a Real time Digital Counter or Clock Circuits using our proposed carry-skip adder. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders design by Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx tool and proposed system implemented in FPGA Spartan 3 XC3S 200 TQ-144.

Keywords: Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.