Design of 64-Bit Multiplier Based on Vedic Mathematics Using VHDL

Abstract: The need of high speed multiplier is increasing day by day on account of recent computer applications. As the multiplication takes considerably more amount of time for its calculation, the computation time must be reduced to get speedy results. To obtain the speedy results, either computation time must be reduced or the pace of the coprocessor must be improved. In this paper we have proposed a high speed 64-bit multiplier making use of Urdhava Tiryakbhyam Sutra of Vedic mathematics. Multiplier is one of the key hardware blocks in most Digital Signal Processing (DSP) systems. Furthermore, design of MAC unit which consists of Multiplier unit, Adder and Accumulator will be implemented. Design, synthesis and simulation of 64-bit MAC unit will be done using XILINX ISE 14.5. Coding of the proposed design will be done in VHDL (Very high Speed Integrated Circuit Hardware Description Language). Combinational path delay obtained for 64-bit Vedic multiplier is 7.970nsec with frequency of 125.467MHz.

Keywords: Urdhava Tiryakbhyam, Vedic Multiplier, XILINX ISE, VHDL.