Design of Power and Area Efficient Approximate Multipliers For Edge Detection Algorithm for Image Processing Application

Abstract: Approximate computing is tentatively applied in some Digital Signal Processing Applications which have an inherent tolerance for Errorneous Result. The Approximate Arithmetic blocks are utilized in them to improve Electrical Performance of these Circuits..The Result Shows that the Proposed Approximate multiplier design accomplish significant reductions in Power dissipation, Delay and Transistor count compared to an Exact accurate Multiplier design with a small loss in accuracy with a HighSpeed Output.This Design is Implemented by Verilog HDL and simulated by Modelsim 6.4c.The Performance is Measured by Xilinix tool Synthesis Process.The Proposed Sobel Edge detection algorithm uses approximation methods to replace the complex operations;This design is done by Matlab and Modelsim.This Proposed Multipliers are Replaced in the Sobel Operator Based Image Edge Detection. The Proposed Compressors Achieve Reduction in delay,power and area Respectively.

Keywords: Approximate Compressors , Image Processing , Sobel Edge Detection , VerilogHDL , Dadda Multiplier.