πŸ“ž +91-7667918914 | βœ‰οΈ ijireeice@gmail.com
International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering
International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2321-2004ISSN Print 2321-5526Since 2013
IJIREEICE meets the suggestive parameters outlined in the latest University Grants Commission (UGC) for peer-reviewed journals, ensuring high standards of research integrity, publication ethics, and academic excellence.
← Back to VOLUME 7, ISSUE 4, APRIL 2019

Error Tolerant and Performance Enhanced TCAM for Network Applications

Dr.S.Kavitha, S.Sreekalpa

πŸ‘ 3 viewsπŸ“₯ 0 downloads
Share: 𝕏 f in ✈ βœ‰
Abstract: Content Addressable Memory (CAM) is a type of solid-state memory in which data are accessed by their contents rather than physic al locations. Ternary Content Addressable Memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high- reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. The proposed work uses a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial keys and parity based logic for search time reduction. The proposed TCAM corrects multiple bit-flip errors and enhances the tolerance of the TCAM against soft errors. TCAM detects multiple- bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and TCAM refreshes the TCAM words by using the backup ECC-SRAM. The proposed CAM also uses parity an extra one-bit segment, derived from the actual data bits. We only obtain the parity bit, i.e., odd or even number of β€œ1”s. This additional parity bit reduces the sensing delay and boosts the driving strength of the 1-mismatch case by half. The hardware overhead of the proposed TCAM is small due to the use of a single TCAM. The parity based TCAM can be easily implemented and is useful for fault-tolerant packet classifiers.

Keywords: TCAM, Multi-bit errors, ATM, SRAM, Parity

How to Cite:

[1] Dr.S.Kavitha, S.Sreekalpa, β€œError Tolerant and Performance Enhanced TCAM for Network Applications,” International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2019.7411

Creative Commons License This work is licensed under a Creative Commons Attribution 4.0 International License.