Low – Power and Error Tolerant Multi – Precision Approximate Multipliers using Voltage and Frequency Management Unit

Abstract: Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. The proposed method uses a novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. The approximate compressors are a key element in the design of power-efficient approximate multipliers, the number of faulty rows in the compressor’s truth table is significantly reduced by encoding its inputs using generate and propagate signals. Further it is converted to Multi Precision (MP) reconfigurable multiplier that incorporates variable precision, Parallel Processing (PP), razor- based Dynamic Voltage Scaling (DVS), and dedicated MP operands scheduling to provide optimum performance for a variety of operating conditions. All of the building blocks of the proposed reconfigurable multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. Given the user’s requirements (e.g., throughput), a dynamic voltage/frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Based on this improved compressor, two 4×4 multipliers are designed with different accuracies and then are used as building blocks for scaling up to 16×16 and 32×32 multipliers. Comparison with previously presented approximated multipliers shows that the proposed circuits provide better power or speed for a target precision.

Keywords: Approximate computing, Compressors, Multi-precision, Image processing