Low Power Bist Implementation of Test Pattern Generation Based on Accumulator

Abstract: The hardware overhead and fault coverage of a circuit is an important problem in integrated circuits and systems. To overcome this problem pseudorandom built-in-self-test (BIST) generators have been widely utilized to test integrated circuits and systems. A Pseudorandom pattern generator (PRPG) is used for generating test patterns (TPG). A weighted Pseudorandom built-in-self-test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. The test patterns are generated automatically (ATPG) for a benchmark circuit by using 3-weight pattern generator. The 3-weight WRBIST is used to reduce the test sequence lengths by improving detection probabilities of random pattern resistant faults (RPRF). So, in this part of project maximum numbers of faults are covered with automatic test pattern generation.

Keywords: ATPG - Automatic Test Pattern Generation, BIST- Built In Self-Test, RPRF- Random Pattern Resistant Fault, LT RTPG – Low transition Random Test Pattern Generation, LFSR – Linear Feedback Shift Register, WR BIST- Weighted Random