Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G4-FET and Gate-All-Around (GAA) MOSFETs

Md. Rakibul Alam; Md. Rais Uddin Mollah; Md. Ferdous Khan

doi:10.17148/IJIREEICE.2019.7301

← Back to VOLUME 7, ISSUE 3, MARCH 2019

Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G4-FET and Gate-All-Around (GAA) MOSFETs

Md. Rakibul Alam, Md. Rais Uddin Mollah, Md. Ferdous Khan

Downloads: Download PDF|DOI: 10.17148/IJIREEICE.2019.7301

👁 1 view📥 0 downloads

Abstract: The performance of fully-depleted Silicon-On-Insulator (SOI) Four Gate Transistor (G4-FET) and Gate-All- Around (GAA) MOSFETs are investigated. Threshold voltage, Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL), maximum drain current are calculated and compared.

Keywords: Silicon-on-Insulator (SOI), Four Gate Transistor (G4-FET), Gate-All-Around (GAA), Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL)

How to Cite:

[1] Md. Rakibul Alam, Md. Rais Uddin Mollah, Md. Ferdous Khan, “Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G4-FET and Gate-All-Around (GAA) MOSFETs,” International Journal of Innovative Research in Electrical, Electronics, Instrumentation and Control Engineering (IJIREEICE), DOI: 10.17148/IJIREEICE.2019.7301

This work is licensed under a Creative Commons Attribution 4.0 International License.