Performance Analysis of Power Gating designs in Low Power VLSI Circuits

Abstract: The growing market for battery- powered mobile electronic systems (e.g., cellular phones, personal digital assistants, etc.) requires the design of micro-electronic circuits with low power dissipation. As the density and complexity of chips continue to increase, the challenge of dissipating power could limit the functionality of computer systems. Especially the nonometer level. Power dissipation uses approximately 35% of the power of the chip. The purpose of this project is to analyze the performance of one of the most reliable approaches to low power design called "Power Gating". The emphasis is only on nanoscale CMOS devices, as this technology is the most widely adopted in current VLSI systems.