Physical Design of NMOS Full Adder using Pass Transistor Logic (PTL)

Abstract: This project presents an NMOS-based Full Adder designed using Pass Transistor Logic to achieve low power, high speed, and compact layout. The design was implemented in Cadence Virtuoso at the 180 nm technology node to minimize the number of transistors and area compared to standard CMOS adders. A restoration circuit ensures full logic levels for reliable performance. Simulation results confirm the improvement in efficiency and make the design suitable for low-power VLSI and embedded applications.

Keywords: NMOS, Pass Transistor Logic, Full Adder, Low Power VLSI, Cadence Virtuoso, CMOS, Integrated Circuit Design.